The present invention relates to a substrate for a semiconductor package and a semiconductor package having the same, and more particularly to a substrate for a semiconductor package that prevents defects that may arise due to positioning error of a solder pattern opening that exposes contact pads.
With advancement of the semiconductor manufacturing technologies, semiconductor packages having semiconductor devices suitable for processing more data in a less time have been studied for development.
Generally, the semiconductor package manufacturing processes include a semiconductor chip manufacturing process for manufacturing semiconductor chips on a high-purity silicon wafer, a die sorting process for checking the semiconductor chips for their electrical integrity, a packaging process for packaging the sorted semiconductor chips, and others.
A chip scale package of recent development targets for a package size that is, for example, only 100% to 105% of the size of chip packaged therein.
One type of the chip scale package is known as a flip chip semiconductor package that reduces the package size by electrically connecting a bump in the semiconductor chip directly to a contact pad in the substrate without using a lead frame.
High integration of a semiconductor chip means much increased number of bumps formed on the chip and therefore a closer interval between the bumps formed on the semiconductor chip.
According to one conventional technique, a plurality of contact pads having micro pitches are arranged on a substrate in a parallel manner, and a solder resist film is formed to cover the plurality of the contact pads. Then, the solder resist film is patterned to form one opening that exposes the plurality of contact pads all together, and a solder paste film covering the contact pads is formed in the opening. After covering the solder paste film in the opening, the solder paste film is melted in order to take advantage of the phenomenon of the solder gathering towards and to be collected at each contact pad, and as such the solder patterns are formed on the contact pads having the micro pitches.
However, when the solder patterns are formed by the aforementioned technique, a problem lies in that the volume of each of the solder patterns formed on the contact pads that are arranged on the outermost part of the substrate is different from the volume of each of the solder patterns formed on the contact pads that are arranged on the non-outermost part of the substrate.
This problem is known to occur due to the errors in the position of the opening being formed by patterning the solder resist film.
Of course, one could propose to better control the position of the opening on the solder resist film in order to control the volume of each solder on each of the contact pads arranged on the outermost part of the substrate.
However, unavoidable positional errors will most likely (if not inevitably) occur when forming the opening by patterning the solder resist film, as such it would be difficult to precisely control the volume of each of the solder patterns of the contact pads arranged on the outermost part of the substrate. This causes defects when bumping the chip bumps to the contact pads.